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GUP PY/2011/01171

The performance of very large-scale integration (VLSI) circuits depends on the interconnected routing in the circuits. VLSI routing, wire sizing, buffer sizing, and buffer insertion are techniques to improve power dissipation, area usage, noise, crosstalk, and time delay. Without considering buffer insertion, the shortest path routing is assumed having the minimum delay and better performance. However, the interconnect delay can be further improved if buffers are inserted at proper locations along the routing path.

Particle Swarm Optimization Particle swarm optimization (PSO) is a population based stochastic optimization technique developed by Dr. Eberhart and Dr. Kennedy in 1995, inspired by social behavior of bird flocking or fish schooling. PSO shares many similarities with evolutionary computation techniques such as Genetic Algorithms (GA). The algorithm is initialized with a population of random solutions and searches for optima by updating generations. However, unlike GA, PSO has no evolution operators such as crossover and mutation. In PSO, the potential solutions, called particles, 'fly' through the problem space by following the current optimum particles. Compared to GA, the advantages of PSO are that PSO is easy to implement and there are few parameters to adjust. PSO has been successfully applied in many areas: function optimization, artificial neural network training, fuzzy system control, and other area where GA can be applied.

Hence, this research proposal proposes a heuristic technique to simultaneously find the optimal routing path and buffer location for minimal interconnect delay in VLSI based on particle swarm optimization (PSO). The location of doglegs is employed to model the particles that represent the routing solutions in VLSI. The performance of the proposed approach will be compared with the existing approaches such as S-RABILA and genetic algorithm-based approach
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